Where Activation Sparsity and KV-Cache Sparsity Cross in LLM Decoding

## Episode Summary

In this episode, we cover:

- **Where Activation Sparsity and KV-Cache Sparsity Cross in LLM Decoding** (arXiv)

- **U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC** (arXiv)

- **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch)

- **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - spectrum.ieee.org** (google_riscv)

- **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - cnx-software.com** (google_riscv)

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*Sponsored by Ada, Ago Consulting, and Zen Semiconductor*