DDR Compliance Simulation in Seconds, Not Days

On this episode of the Altium OnTrack Podcast, host Zach Peterson talks with Ben Dannan, founder of Signal Edge Solutions and DesignCon Engineer of the Year, and Tyler Huddleston, SI/PI engineer, about a problem every high-speed designer knows too well: DDR compliance simulation that can take 24 hours to several days per interface. They walk through why the traditional Keysight ADS Memory Designer compliance flow is so slow, how false positives creep into JEDEC compliance results, and why running corners across fast, typical, and slow for a full DQ and command/address bus can balloon into nine-plus simulations and weeks of waiting.

Ben and Tyler then demo their new tool, MEM Check Pro, which ingests the raw HDF5 waveform data you already generated and returns full DDR4, DDR5, and LPDDR compliance results in under a minute — live on camera. Along the way the conversation digs into the real signal integrity and power integrity challenges behind modern data-center and aerospace hardware: thick backplanes and backside power delivery, managing loop inductance and PDN-to-PDN crosstalk, IBIS model quality, advanced laminate systems, and choosing the right decoupling capacitors. It's a practical look at how to trade days of simulation for seconds without giving up confidence in your results.

📚 More from this Episode:- Signal Edge Solutions: https://www.signaledgesolutions.com/ - Ben Dannan on LinkedIn: https://www.linkedin.com/in/benjamin-dannan/- Keysight PathWave ADS: https://www.keysight.com/us/en/products/software/pathwave-design-software/pathwave-advanced-design-system.html

💡 Watch Next:- xSignals for DDR3 and DDR4 in Altium Designer | High-Speed Design: https://www.youtube.com/watch?v=7JJ8652UozI- Capacitor Self Resonance | Power Integrity in PCB Design: https://www.youtube.com/watch?v=kvWHQmSML-4- How to Route High-Speed Designs in Altium Designer: https://www.youtube.com/watch?v=KuESxLS2Lno

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